1. Field of the Invention
The present invention relates to data recovery systems and, in particular, to the testing and characterization of the "window-time" specification for a phase locked loop (PLL) integrated circuit which is utilized for data synchronization.
2. Discussion of the Prior Art
From a "black box" standpoint, a phase looked loop data synchronizer receives a single channel data stream and outputs two channels of synchronous signals. The first channel is a replica of the input data. The second channel is a periodic clock which is synchronized to the input data.
This type of PLL establishes a "window" around the expected position of bits within the data stream. It permits a fair degree of random displacement, i.e. jitter, of the individual bits within the boundaries of the window with no apparent effect on the accuracy of the recovery of perturbed data.
To achieve optimum data recovery performance, a PLL is designed with a maximum available window width and with a specified minimum skew between the nominal data bit position and its corresponding decode window center.
In order to ensure that a PLL device is operating within its specification, a suitable measurement is required which forces a data test pattern to displace from its ideal position to ascertain the magnitude of displacement the PLL device can tolerate relative to its specified detection window.
Previous techniques for evaluating discrete or hybrid forms of PLL circuitry window margins; that is, the available window width for the data bit and the associated phase margin, i.e. the data pulse position from the theoretical center of its data window) involve elaborate test setups which include pattern, function and pulse generators together with software or firmware required to support programmability for changing to different test vectors. In-system testing, which is the typical technique used within the industry for testing PLLs, is a system rather than a device oriented procedure. Additionally, the conventionally used techniques rely on dynamic test patterns to simulate in-system conditions. This method depends on the ac characteristic of the circuitry. It also depends on the codes, the type of worst-case patterns employed and the bias conditions selected by different users.
A better approach is a "set-up on demand" arrangement. According to this technique, either single-bit or multiple-byte long test patterns are employed. Usually, some specific "worst-case" patterns are incorporated to determine the probablistic distribution of data error accumulated in a given test sequence. The problems with these "on demand" type of arrangements are non-standardized test patterns and a dependence on the data rate, coding method and passive support components used. These techniques are not suitable for data comparison unless the hardware and firmware are uniform and tightly controlled.